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The circuit shown in Figure 8-3 represents a(n) ________. Question 1 options: synchronous BCD decade counter BCD-to-decimal decoder synchronous four-bit binary counter asynchronous BCD decade counter Question 2 A MOD 12 and a MOD 10 counter are cascaded. The input clock frequency is 60 MHz. Determine the counter output frequency. Question 2 options: 1,500 kHz 5 MHz 6 MHz 500 kHz Question 3 What is the output state of a MOD-64 counter after 92 input pulses if the starting state is 000000? Question 3 options: 0101102 0111102 1001002 0111002 Question 4 Which of the following best describes the characteristics of a MOD-16 counter? Question 4 options: Sixteen possible counts, a maximum count of 1510, and frequency division by a factor of eight Eight possible counts, a maximum count of 710 and frequency division by a factor of eight Eight possible counts, a minimum count of 710, and frequency division by a factor of sixteen Sixteen possible counts, a maximum count of 1510, and frequency division by a factor of sixteen